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Job Title: JR0193721 - Ocotillo Technology Fabrication Senior Advanced Lithography Process Engineer
Company Name: Intel
Location: Phoenix, AZ
Position Type: Full Time
Post Date: 08/01/2022
Expire Date: 09/30/2022
Job Categories: Arts, Entertainment, and Media, Engineering, Government and Policy, Healthcare, Practitioner and Technician, Installation, Maintenance, and Repair, Manufacturing and Production, Military, Quality Control, Research & Development, Medical, Environmental, Energy / Utilities
Job Description
JR0193721 - Ocotillo Technology Fabrication Senior Advanced Lithography Process Engineer

As an Intel OTF Litho Process Engineer, you'll join a team helping to develop the most efficient means for semiconductor manufacturing, enabling microprocessors to yield higher and be manufactured more affordably. Process engineers, along with yield and equipment engineers, take responsibility for monitoring and controlling wafer fabrication and product performance including managing tool productivity and maintenance, conducting data analysis to improve processes, and managing quality control points to target.  A process engineer has responsibilities that touch multiple pillars within the department including safety, quality, cost, output & cycle time, training, and productivity – driving systematics improvements in each of these vectors.   A process engineer is expected to support segment team activities to enable parametric and defectivity matching on the product and improvement across different sectors of the process flow.  A process engineer may also be responsible for supporting cross-functional and cross-department activities to enable parametric and defectivity matching and improvement.  In addition to driving results in these spaces, a process engineer is expected to be a role model for the culture and set the standard for expectations to living the culture.  Training, development, and mentoring of junior engineers is also an expectation as we develop the team for future challenges.

Responsibilities may include:

  • Ensuring sufficient safety and cleanliness of your area and ensuring copy exactly matching of eqp configuration, parameters, and targeting to the standard

  • Regular review of metrics related to your tool and area’s quality output

  • Driving continuous improvement in the health and matching of your toolset by developing, maintaining, and executing an improvement roadmap across all the different factory pillars

  • Applying model-based problem solving to identify root cause of tool or process mismatches from target, and then developing solutions to problems utilizing formal education and judgment

  • Conducting tests and measurements to determine control over such variables as litho imaging defects levels, thickness, temperature, density, pressure, and viscosity influences on wafer processing

  • For new technology start-ups, managing tool installations, conversions, and qualifications plus delivering ½ sigma matched performance on critical silicon

  • Mentoring technicians and junior engineers across all shifts to deliver best-in-class results for path availability, cycle time, defects and parametric performance

  • Ability to develop improved quality and yield sustaining systems for engineering teams based on strong understanding of multivariate process interactions.

The ideal candidate should have a subset of the following traits:

  • Technical expertise on photolithography scanner platforms and be able to provide technical direction on Lithography quality issues, lithography matching performance and Lithography yield improvement. 

  • Expertise with lithography clean track equipment and function, including dispense system knowledge and the ability to identify, troubleshoot, and resolve dispense-related defect sources

  • Expertise with lithography chemicals – resist and anti-reflective coatings – and how they interact with filter media materials and pore-size

  • Clear understanding of how the lithography clean track impacts the overall chip building process within litho and with upstream and downstream operations

  • Expertise with troubleshooting inline integrated defect sources and developing root cause solutions at the tool level

  • Familiarity with variable and fixed cost reduction techniques as they relate to tool fingerprint and process recipe conditions on a lithography clean track   

  • Expertise in Mask shop processing with focus on latest manufacturing process technology and advanced cleans process, photo induced defect mode detection, phase shift and advanced mask imaging techniques, frame layout techniques and defect classifications.

  • Expertise in system development to help model Reticle changes and monitor reticle health.

  • Demonstrated capability of working in a high performing team culture which includes: setting high expectations, driving accountability to those expectations with a high sense of urgency, role modeling the desired culture, possess excellent teamwork and leadership skills, demonstrated problem solving and prioritization skills, and driving high performance maintenance goals for the group.

  • Ability to use data to influence factory and virtual factory direction

  • Excellent listening, written and verbal communication, an ability to deal with ambiguity in defining activities and direction, and commitment to task. 

  • Ability to work independently and manage stakeholders

  • Capable of articulating data and projects to senior management

  • High motivation with a strong work ethic

  • Strong analytical mind with problem solving skills

  • Ability to build interactions with internal Intel support groups and internal functional areas to support and drive an aligned Lithography business result

  • Ability to influence change across the virtual factory networks


Minimum requirements:

  • Candidate must possess at a minimum a Bachelor of Science degree in a related science or engineering field with 7 years of process engineering experience in semiconductor wafer fabrication.
  • Ideal candidate will have a minimum of 5 years of lithography experience in any of the following :
    • Process flow, equipment troubleshooting.
    • Interacting with vendor field service engineering support and manufacturing/engineering technicians on toolsets.
    • Providing technical direction on quality issues.
    • Advanced data analysis.
    • Lithography theory
    • Knowledge of lithography track equipment, including recipe development and defect troubleshooting techniques  
    • Technical expertise on photolithography reticle equipment and risk model.
    • Developing novel inline detection techniques to help predict end of line failures based on advanced understanding of semiconductor process flow as well as end of line Sort bin failure modes, Etest and Failure analysis techniques.
    • Knowledge of EUV, immersion, or advanced lithography processes and equipment configurations

Preferred Qualifications:

  • Technical expertise within Semiconductor Processing Engineering and be able to provide technical direction on Lithography quality issues, Lithography matching performance and Lithography yield improvement issues.
  • Understanding of lithography manufacturing process steps and ability to understand interactions with incoming and outgoing process modules.
  • Knowledge of immersion lithography processes and equipment configurations
  • Equipment knowledge on TEL ProV and ProZ Lithius platforms
  • Technical expertise on photolithography Reticle Equipment and risk models and be able to provide technical direction on quality issues, lithography matching performance and Lithography yield improvement. 
  • Understanding of Reticle print risks and ability to understand interactions with lithography patterning equipment such as EUV and environmental and processing impacts.
  • Knowledge of immersion lithography processes and EUV processing and reticle interactions.  
  • Experience working in a Mask shop with focus on processing and yield.
  • Knowledge of Manufacturing science, Capacity Metrics, In-line and EOL defect and excursion prevention/response
  • Experience in leading senior, cross function/cross organization teams
  • Experience in Data analysis (JMP, SPC, MATLAB, Mathematica) and Design of experiment (DOE) principles
  • Previous or current Intel OTF Process Engineering experience, and knowledge of Intel OTF systems and processes will be considered a plus factor when evaluating candidates for this position.
  • Having a strong working relationship with PTD is considered a plus.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Company Name: Intel
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